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Sequential Logic Circuit Quiz
1. How is a J-K flip-flop made to toggle?
J = 0, K = 0
J = 1, K = 0
J = 0, K = 1
J = 1, K = 1
Submit
2.On a master-slave flip-flop, when is the master enabled?
when the gate is LOW
when the gate is HIGH
both of the above
neither of the above
Submit
3. Which of the following is correct for a gated D flip-flop?
The output toggles if one of the inputs is held HIGH.
Only one of the inputs can be HIGH at a time.
The output complement follows the input when enabled.
Q output follows the input D when the enable is HIGH.
Submit
4. When is a flip-flop said to be transparent?
when the Q output is opposite the input
when the Q output follows the input
when you can see through the IC packaging
Submit
5.Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
TRUE
FALSE
Submit
6.A J-K flip-flop is in a "no change" condition when ________.
J = 1, K = 1
J = 1, K = 0
J = 0, K = 1
J = 0, K = 0
Submit
7. Which of the following describes the operation of a positive edge-triggered D flip-flop?
If both inputs are HIGH, the output will toggle.
The output will follow the input on the leading edge of the clock.(
When both inputs are LOW, an invalid state exists.
The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
Submit
8.What does the triangle on the clock input of a J-K flip-flop mean?
level enabled
edge-triggered
Submit
9.The toggle conditions in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.
opposite, active clock edge
inverted, positive clock edge
quiescent, negative clock edge
reset, synchronous clock edge
Submit
10.What is the hold condition of a flip-flop?
both S and R inputs activated
no active S or R input
only S is active
only R is active
Submit
11.Why are the S and R inputs of a gated flip-flop said to be synchronous?
They must occur with the gate.
They occur independent of the gate.
Submit
12.Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.
TRUE
FALSE
Submit
13.Which of the following is not generally associated with flip-flops?
Hold time
Propagation delay time
Interval time
Set up time
Submit
14.Edge-triggered flip-flops must have:
very fast response times
at least two inputs to handle rising and falling edges
positive edge-detection circuits
negative edge-detection circuits
Submit
Your Answer is CORRECT.The Answer is D
A.J = 0, K = 0
B.J = 1, K = 0
C.J = 0, K = 1
D.J = 1, K = 1
Next
Your Answer is CORRECT.The Answer is B
A.when the gate is LOW
B.when the gate is HIGH
C.both of the above
D.neither of the above
Next
Your Answer is CORRECT.The Answer is D
A.The output toggles if one of the inputs is held HIGH.
B.Only one of the inputs can be HIGH at a time.
C.The output complement follows the input when enabled.
D.Q output follows the input D when the enable is HIGH.
Next
Your Answer is CORRECT.The Answer is B
A.when the Q output is opposite the input
B.when the Q output follows the input
C.when you can see through the IC packaging
Next
Your Answer is CORRECT.The Answer is B
A.TRUE
B.FALSE
Next
Your Answer is CORRECT.The Answer is D
A.J = 1, K = 1
B.J = 1, K = 0
C.J = 0, K = 1
D.J = 0, K = 0
Next
Your Answer is CORRECT.The Answer is B
A.If both inputs are HIGH, the output will toggle.
B.The output will follow the input on the leading edge of the clock.
C.When both inputs are LOW, an invalid state exists.
D.The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
Next
Your Answer is CORRECT.The Answer is B
A.A > B =1, A < B = 0 , A < B = 1
B.A > B = 0, A < B = 1 , A = B = 0
C.A > B = 1, A < B = 0 , A = B = 0
D.A > B = 0 , A < B = 1 , A = B = 1
Next
Your Answer is CORRECT.The Answer is A
A. opposite, active clock edge
B. inverted, positive clock edge
C. quiescent, negative clock edge
D. reset, synchronous clock edge
Next
Your Answer is CORRECT.The Answer is B
A.both S and R inputs activated
B.no active S or R input
C.only S is active
D.only R is active
Next
Your Answer is CORRECT.The Answer is A
A.They must occur with the gate.
B.They occur independent of the gate.
Next
Your Answer is CORRECT.The Answer is B
A.TRUE
B.FALSE
Next
Your Answer is CORRECT.The Answer is C
A.Hold time
B.Propagation delay time
C.Interval time
D.Set up time
Next
Your Answer is CORRECT.The Answer is C
A.very fast response times
B.at least two inputs to handle rising and falling edges
C.positive edge-detection circuits
D.negative edge-detection circuits
Next
Your Answer is WRONG.The Answer is D
A.J = 0, K = 0
B.J = 1, K = 0
C.J = 0, K = 1
D.J = 1, K = 1
Next
Your Answer is WRONG.The Answer is B
A.when the gate is LOW
B.when the gate is HIGH
C.both of the above
D.neither of the above
Next
Your Answer is WRONG.The Answer is D
A.The output toggles if one of the inputs is held HIGH.
B.Only one of the inputs can be HIGH at a time.
C.The output complement follows the input when enabled.
D.Q output follows the input D when the enable is HIGH.
Next
Your Answer is WRONG.The Answer is B
A.when the Q output is opposite the input
B.when the Q output follows the input
C.when you can see through the IC packaging
Next
Your Answer is WRONG.The Answer is B
A.TRUE
B.FALSE
Next
Your Answer is WRONG.The Answer is D
A.J = 1, K = 1
B.J = 1, K = 0
C.J = 0, K = 1
D.J = 0, K = 0
Next
Your Answer is WRONG.The Answer is B
A.If both inputs are HIGH, the output will toggle.
B.The output will follow the input on the leading edge of the clock.
C.When both inputs are LOW, an invalid state exists.
D.The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
Next
Your Answer is WRONG.The Answer is B
A.A > B =1, A < B = 0 , A < B = 1
B.A > B = 0, A < B = 1 , A = B = 0
C.A > B = 1, A < B = 0 , A = B = 0
D.A > B = 0 , A < B = 1 , A = B = 1
Next
Your Answer is WRONG.The Answer is A
A. opposite, active clock edge
B. inverted, positive clock edge
C. quiescent, negative clock edge
D. reset, synchronous clock edge
Next
Your Answer is WRONG.The Answer is B
A.both S and R inputs activated
B.no active S or R input
C.only S is active
D.only R is active
Next
Your Answer is WRONG.The Answer is A
A.They must occur with the gate.
B.They occur independent of the gate.
Next
Your Answer is WRONG.The Answer is B
A.TRUE
B.FALSE
Next
Your Answer is WRONG.The Answer is C
A.Hold time
B.Propagation delay time
C.Interval time
D.Set up time
Next
Your Answer is WRONG.The Answer is C
A.very fast response times
B.at least two inputs to handle rising and falling edges
C.positive edge-detection circuits
D.negative edge-detection circuits
Next